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ds96dz80301 (11/96) p r e l i m i n a r y 1-1 1 p reliminary c ustomer p rocurement s pecification z86c02/e02/l02 1 l ow -c ost , 512-b yte rom m icrocontrollers features n 18-pin dip and soic packages n 0 c to 70 c standard temperature ?0 c to 105 c extended temperature (z86c02/e02 only) n 3.0v to 5.5v operating range (z86c02) 4.5v to 5.5v operating range (z86e02) 2.0v to 3.9v operating range (z86l02) n 14 input / output lines n five vectored, prioritized interrupts from five different sources n two on-board comparators n software enabled watch-dog timer (wdt) n programmable interrupt polarity n two standby modes: stop and halt n low-voltage protection n rom mask/otp options: low-noise (z86c02/e02 only) rom protect auto latch permanent watch-dog timer (wdt) rc oscillator (z86c02/l02 only) 32 khz operation (z86c02/l02 only) n one programmable 8-bit counter/timer with a 6-bit programmable prescaler n power-on reset (por) timer n on-chip oscillator that accepts rc, crystal, ceramic resonator, lc, or external clock drive (c02/l02 only) n on-chip oscillator that accepts rc or external clock drive (z86e02 sl1903 only) n on-chip oscillator that accepts crystal, ceramic resonator, lc, or external clock drive (z86e02 only) n clock-free wdt reset n low-power consumption (50mw) n fast instruction pointer (1.5 m s @ 8 mhz) n fourteen digital inputs at cmos levels; schmitt-triggered general description zilog's z86c02/e02/l02 microcontrollers (mcus) are members of the z8 single-chip mcu family, which offer easy software/hardware system expansion. for applications demanding powerful i/o capabilities, the mcu's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel i/o. one on-chip counter/timer, with a large number of user-se- lectable modes, off-load the system of administering real- time tasks such as counting/timing and i/o data communi- device rom (kb) ram* (bytes) speed (mhz) auto latch permanent wdt z86c02 512 61 8 optional optional z86e02 512 61 8 optional optional z86l02 512 61 8 optional optional note: *general-purpose
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-2 p r e l i m i n a r y ds96dz80301 (11/96) general description (continued) cations. additionally, two on-board comparators process analog signals with a common reference voltage (figure 1). note: all signals with a preceding front slash, "/", are ac- tive low, e.g.: b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions be- low: connection circuit device power v cc v dd ground gnd v ss figure 1. z86c02/e02/l02 functional block diagram port 3 counter/ timer interrupt control two analog comparators port 2 i/o (bit programmable) flag register pointer general-purpose register file machine timing & inst. control program memory program counter vcc gnd xtal port 0 i/o input alu
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-3 p r e l i m i n a r y ds96dz80301 (11/96) general description (continued) pin descriptions figure 2. eprom programming mode block diagram z8 mcu address counter address mux data mux z8 port2 option bits eprom pgm mode logic d7-d0 d7-d0 d7-d0 a10-a0 a10-a0 a10-a0 3 bits clear p00 clock p01 epm p32 /ce xt1 /pgm p02 vpp p33 /oe p31 figure 3. 18-pin standard mode con?uration 1 2 9 3 4 5 6 7 8 18 17 16 15 14 13 12 11 10 p23 p22 p33 p21 p20 gnd p02 p01 p00 p24 p25 p32 p26 p27 vcc xtal2 xtal1 p31 standard mode table 1. 18-pin standard mode identi?ation pin # symbol function direction 1-4 p24-p27 port 2, pins 4, 5, 6, 7 in/output 5v cc power supply 6 xtal2 crystal oscillator clock output 7 xtal1 crystal oscillator clock input 8 p31 port 3, pin 1, an1 input 9 p32 port 3, pin 2, an2 input 10 p33 port 3, pin 3, ref input 11-13 p00-p02 port 0, pins 0, 1, 2 in/output 14 gnd ground 15-18 p20-p23 port 2, pins 0, 1, 2, 3 in/output
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-4 1 figure 4. 18-pin eprom mode con?uration table 2. 18-pin eprom mode identi?ation pin # symbol function direction 1-4 d4-d7 data 4, 5, 6, 7 in/output 5 vcc power supply 6 nc no connection 7 /ce chip enable input 8 /oe output enable input 9 epm eprom program mode input 10 vpp program voltage input 11 clear clear clock input 12 clock address input 13 /pgm program mode input 14 gnd ground 15-18 d0-d3 data 0, 1, 2, 3 in/output 1 2 9 3 4 5 6 7 8 18 17 16 15 14 13 12 11 10 d3 d2 vpp d1 d0 gnd /pgm clock clear d4 d5 epm d6 d7 vcc n/c /ce /oe eprom mode figure 5. 18-pin soic con?uration table 3. 18-pin soic pin identi?ation standard mode pin # symbol function direction 1-4 p24-p27 port 2, pins 4,5,6,7 in/output 5 vcc power supply 6 xtal2 crystal osc. clock output 7 xtal1 crystal osc. clock input 8 p31 port 3, pin 1, an1 input 9 p32 port 3, pin 2, an2 input 10 p33 port 3, pin 3, ref input 11-13 p00-p02 port 0, pins 0,1,2 in/output 14 gnd ground 15-18 p20-p23 port 2, pins 0,1,2,3 in/output 118 p24 p27 vcc xtal2 xtal1 p31 p32 p23 p22 p21 p20 gnd p02 p01 p00 p33 p25 p26 2 3 4 5 6 7 8 9 17 16 15 14 13 12 11 10
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-5 1 absolute maximum ratings notes: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for an extended period may affect device reliability. total power dissipation should not exceed 462 mw for the package. power dissipation is calculated as follows: 1. this applies to all pins except where otherwise noted. 2. maximum current into pin must be 600 m a. there is no input protection diode from pin to v dd . 3. this excludes pin 6 and pin 7. 4. device pin is not at an output low state. total power dissipation = v dd x [i dd ?(sum of i oh )] + sum of [(v dd ?v oh ) x i oh ] + sum of (v 0l x i 0l ) standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to ground. positive current flows into the referenced pin (fig- ure 6). capacitance t a = 25 c, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to gnd. parameter min max units ambient temperature under bias ?0 +105 c storage temperature ?5 +150 c voltage on any pin with respect to v ss [note 1] ?.7 +12 v voltage on v dd pin with respect to v ss ?.3 +7 v voltage on pin 7 with respect to v ss [note 2] (z86c02/l02) ?.7 v dd +1 v voltage on pin 7,8,9,10 with respect to v ss [note 2] (z86e02) ?.7 v dd +1 v total power dissipation 462 mw maximum allowed current out of v ss 300 ma maximum allowed current into v dd 270 ma maximum allowed current into an input pin [note 3] ?00 +600 m a maximum allowed current into an open-drain pin [note 4] ?00 +600 m a maximum allowed output current sinked by any i/o pin 20 ma maximum allowed output current sourced by any i/o pin 20 ma maximum allowed output current sinked by port 2, port 0 80 ma maximum allowed output current sourced by port 2, port 0 80 ma figure 6. test load diagram from output under test 150 pf parameter min max input capacitance 0 15 pf output capacitance 0 20 pf i/o capacitance 0 25 pf
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-6 p r e l i m i n a r y ds96dz80301 (11/96) dc electrical characteristics z86c02 t a = 40 c to +105 c t a = 0 c to +70 c typical sym. parameter v cc [4] min max @ 25 c units conditions notes v ch clock input high voltage 3.0v 0.8 v cc v cc +0.3 1.7 v driven by external clock generator 5.5v 0.8 v cc v cc +0.3 2.8 v driven by external clock generator v cl clock input low voltage 3.0v v ss ?.3 0.2 v cc 0.8 v driven by external clock generator 5.5v v ss ?.3 0.2 v cc 1.7 v driven by external clock generator v ih input high voltage 3.0v 0.7 v cc v cc +0.3 1.8 v [1] 5.5v 0.7 v cc v cc +0.3 2.8 v [1] v il input low voltage 3.0v v ss ?.3 0.2 v cc 0.8 v [1] 5.5v v ss ?.3 0.2 v cc 1.5 v [1] v oh output high voltage 3.0v v cc ?.4 3.0 v i oh = ?.0 ma [5] 5.5v v cc ?.4 4.8 v i oh = ?.0 ma [5] 3.0v v cc ?.4 3.0 v low noise @ i oh = ?.5 ma 5.5v v cc ?.4 4.8 v low noise @ i oh = ?.5 ma v ol1 output low voltage 3.0v 0.8 0.2 v i ol = +4.0 ma [5] 5.5v 0.4 0.1 v i ol = +4.0 ma [5] 3.0v 0.8 0.2 v low noise @ i ol = 1.0 ma 5.5v 0.4 0.1 v low noise @ i ol = 1.0 ma v ol2 output low voltage 3.0v 1.0 0.8 v i ol = +12 ma [5] 5.5v 0.8 0.3 v i ol = +12 ma [5] v offset comparator input offset voltage 3.0v 25 10 mv 5.5v 25 10 mv v lv v cc low voltage auto reset v 2.2 2.8 2.6 v [9] 2.0 3.0 2.6 v [10] i il input leakage (input bias current of comparator) 3.0v ?.0 1.0 m av in = 0v, v cc 5.5v ?.0 1.0 m av in = 0v, v cc i ol output leakage 3.0v ?.0 1.0 m av in = 0v, v cc 5.5v ?.0 1.0 m av in = 0v, v cc v vicr comparator input common mode voltage range v ss ?.3 v cc ?.0 v [9] v ss ?.3 v cc ?.5 v [10]
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-7 1 dc characteristics z86c02 t a = 40 c to+105 c t a = 0 c to +70 c typical sym. parameter v cc [4] min max @ 25 c units conditions notes i cc supply current 3.0v 3.5 1.5 ma @ 2 mhz [5,6,7] 5.5v 7.0 3.8 ma @ 2 mhz [5,6,7] 3.0v 8.0 3.0 ma @ 8 mhz [5,6,7] 5.5v 11.0 4.4 ma @ 8 mhz [5,6,7] i cc1 standby current (halt mode) 3.0v 2.5 0.7 ma @ 2 mhz [5,6,7] 5.5v 4.0 2.5 ma @ 2 mhz [5,6,7] 3.0v 4.0 1.0 ma @ 8 mhz [5,6,7] 5.5v 5.0 3.0 ma @ 8 mhz [5,6,7] i cc supply current (low noise mode) 3.0v 3.5 1.5 ma @ 1 mhz [5,6,7] 5.5v 7.0 3.8 ma @ 1 mhz [5,6,7] 3.0v 5.8 2.5 ma @ 2 mhz [5,6,7] 5.5v 9.0 4.0 ma @ 2 mhz [5,6,7] 3.0v 8.0 3.0 ma @ 4 mhz [5,6,7] 5.5v 11.0 4.4 ma @ 4 mhz [5,6,7] i cc1 standby current (low noise halt mode) 3.0v 2.5 0.7 ma @ 1 mhz [6,7,8] 5.5v 4.0 2.5 ma @ 1 mhz [6,7,8] 3.0v 3.0 0.9 ma @ 2 mhz [6,7,8] 5.5v 4.5 2.8 ma @ 2 mhz [6,7,8] 3.0v 4.0 1.0 ma @ 4 mhz [6,7,8] 5.5v 5.0 3.0 ma @ 4 mhz [6,7,8] i cc2 standby current (stop mode) 3.0v 10 1.0 m a [6,7,8,9] 3.0v 20 1.0 m a [6,7,8,10] 5.5v 10 1.0 m a [6,7,8,9] 5.5v 20 1.0 m a [6,7,8,10] i all auto latch low current 3.0v 12 3.0 m a 0v < v in < v cc 5.5v 32 16 m a 0v < v in < v cc i alh auto latch high current 3.0v ? -1.5 m a 0v < v in < v cc 5.5v ?6 -8.0 m a 0v < v in < v cc notes: 1. ort 0, 2, and 3 only. 2. v ss = 0v = gnd. 3. the device operates down to v lv the minimum operational v cc is determined on the value of the voltage v lv at the ambient temperature. 4. v cc = 3.0v to 5.5v, typical values measured at v cc = 3.3v and v cc = 5.0v. 5. standard mode (not low emi mode). 6. inputs at v cc or v ss , outputs unloaded. 7. halt mode and low emi mode. 8. wdt not running. 9. t a = 0?c to 70?c. 10. t a = 40?c to 105?c.
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-8 p r e l i m i n a r y ds96dz80301 (11/96) dc characteristics z86l02 t a = 0 c to +70 c typical sym. parameter v cc [4] min max @ 25 c units conditions notes v ch clock input high voltage 2.0v 0.9 v cc v cc +0.3 v driven by external clock generator 3.9v 0.9 v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0v v ss ?.3 0.1 v cc v driven by external clock generator 3.9v v ss ?.3 0.1 v cc v driven by external clock generator v ih input high voltage 2.0v 0.9 v cc v cc +0.3 v [1] 3.9v 0.9 v cc v cc +0.3 v [1] v il input low voltage 2.0v v ss ?.3 0.1 v cc v [1] 3.9v v ss ?.3 0.1 v cc v [1] v oh output high voltage 2.0v v cc ?.4 3.0 v i oh = ?500 m a [5] 3.9v v cc ?.4 3.0 v i oh = ?00 m a [5] v ol1 output low voltage 2.0v 0.8 0.2 v i ol = +1.0 ma [5] 3.9v 0.4 0.1 v i ol = +1.0 ma [5] v ol2 output low voltage 2.0v 1.0 0.8 v i ol = + 3.0 ma [5] 3.9v 0.8 0.3 v i ol = + 3.0 ma [5] v offset comparator input offset voltage 2.0v 25 10 mv 3.9v 25 10 mv v lv v cc low voltage auto reset 1.4 2.15 v i il input leakage (input bias current of comparator) 2.0v ?.0 1.0 m av in = 0v, v cc 3.9v ?.0 1.0 m av in = 0v, v cc i ol output leakage 2.0v ?.0 1.0 m a v in = 0v, v cc 3.9v ?.0 1.0 m av in = 0v, v cc v vicr comparator input common mode voltage range v ss ?.3 v cc ?.0 v
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-9 1 t a = 0 c to +70 c typical sym parameter v cc [4] min max @ 25 c units conditions notes i cc supply current 2.0v 3.3 ma @ 2 mhz [5,6] 3.9v 6.8 ma @ 2 mhz [5,6] 2.0v 6.0 ma @ 8 mhz [5,6] 3.9v 9.0 ma @ 8 mhz [5,6] i cc1 standby current (halt mode) 2.0v 2.3 ma @ 2 mhz [5,6,7] 3.9v 3.8 ma @ 2 mhz [5,6,7] 2.0v 3.8 ma @ 8 mhz [5,6,7] 3.9v 4.8 ma @ 8 mhz [5,6,7] i cc2 standby current (stop mode) 2.0v 10 1.0 m a [6,7] 3.9v 10 1.0 m a [6,7] i all auto latch low current 2.0v 12 3.0 m a 0v < v in < v cc 3.9v 32 16 m a 0v < v in < v cc i alh auto latch high current 2.0v ? -1.5 m a 0v < v in < v cc 3.9v ?6 -8.0 m a notes: 1. port 0, 2, and 3 only 2. v ss = 0v = gnd.the device operates down to v lv . the minimum operational v cc is determined by the value of the voltage v lv at the ambient temperature. 3. v cc = 2.0v to 3.9v, typical values measured at v cc = 3.3 v. 4. standard mode (not low emi mode). 5. inputs at v cc or v ss , outputs are unloaded. 6. wdt is not running.
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-10 p r e l i m i n a r y ds96dz80301 (11/96) dc characteristics z86e02 t a = ?0 c to +105 c t a = 0 c to +70 c typical sym. parameter v cc [4] min max @ 25 c units conditions notes v ch clock input high voltage 4.5v 0.8 v cc v cc +0.3 2.8 v driven by external clock generator 5.5v 0.8 v cc v cc +0.3 2.8 v driven by external clock generator v cl clock input low voltage 4.5v v ss ?.3 0.2 v cc 1.7 v driven by external clock generator 5.5v v ss 0.3 0.2 v cc 1.7 v driven by external clock generator v ih input high voltage 4.5v 0.7 v cc v cc +0.3 2.8 v 5.5v 0.7 v cc v cc +0.3 2.8 v v il input low voltage 4.5v v ss ?.3 0.2 v cc 1.5 v 5.5v v ss ?.3 0.2 v cc 1.5 v v oh output high voltage 4.5v v cc ?.4 4.8 v i oh = ?.0 ma [5] 5.5v v cc ?.4 4.8 v i oh = ?.0 ma [5] 4.5v v cc ?.4 4.8 v low noise @ i oh = ?.5 ma 5.5v v cc ?.4 4.8 v v ol1 output low voltage 4.5v 0.4 0.1 v i ol = +4.0 ma [5] 5.5v 0.4 0.1 v i ol = +4.0 ma [5] 4.5v 0.4 0.1 v low noise @ i ol = 1.0 ma 5.5v 0.4 0.1 v low noise @ i ol = 1.0 ma v ol2 output low voltage 4.5v 1.0 0.8 v i ol = +12 ma [5] 5.5v 1.0 0.8 v i ol = +12 ma [5] v offset comparator input offset voltage 4.5v 25 10 mv 5.5v 25 10 mv v lv v cc low voltage auto reset 2.6 3.3 3.0 v [9] 2.2 3.6 3.0 v [10] i il input leakage (input bias current of comparator) 4.5v ?.0 1.0 m av in = 0v, v cc 5.5v ?.0 1.0 m av in = 0v, v cc i ol output leakage 4.5v ?.0 1.0 m av in = 0v, v cc 5.5v ?.0 1.0 m av in = 0v, v cc v vicr comparator input common mode voltage range v ss ?.3 v cc ?.0 v [9] v ss ?.3 v cc ?.5 v [10]
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-11 1 t a = ?0 c to +105 c t a = 0 c to +70 c typical sym. parameter v cc [4] min max @ 25 c units conditions notes i cc supply current 4.5v 9.0 3.8 ma @ 2 mhz [5,6] 5.5v 9.0 3.8 ma @ 2 mhz [5,6] 4.5v 15.0 4.4 ma @ 8 mhz [5,6] 5.5v 15.0 4.4 ma @ 1 mhz [5,6] i cc1 standby current (halt mode) 4.5v 4.0 2.5 ma @ 2 mhz [5,6] 5.5v 4.0 2.5 ma @ 2 mhz [5,6] 4.5v 5.0 3.0 ma @ 4 mhz [5,6] 5.5v 5.0 3.0 ma @ 4 mhz [5,6] i cc supply current (low noise mode) 4.5v 9.0 3.8 ma [6] 5.5v 9.0 3.8 ma [6] 4.5v 11.0 4.0 ma @ 2 mhz [6] 5.5v 11.0 4.0 ma @ 2 mhz [6] 4.5v 15.0 4.4 ma @ 4 mhz [6] 5.5v 15.0 4.4 ma @ 4 mhz [6] i cc1 standby current (low noise halt mode) 4.5v 4.0 2.5 ma @ 1 mhz [6,7,8] 5.5v 4.0 2.5 ma @ 1 mhz [6,7,8] 4.5v 4.5 2.7 ma @ 2 mhz [6,7,8] 5.5v 4.5 2.7 ma @ 2 mhz [6,7,8] 4.5v 5.0 3.0 ma @ 4 mhz [6,7,8] 5.5v 5.0 3.0 ma @ 4 mhz [6,7,8] i cc2 standby current (stop mode) 4.5v 10 1.0 m a [6,7,9] 4.5v 20 1.0 m a [6,7,10] 5.5v 10 1.0 m a [6,7,9] 5.5v 20 1.0 m a 6,7,10] i all auto latch low current 4.5v 32 16 m a 0v z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-12 p r e l i m i n a r y ds96dz80301 (11/96) ac electrical characteristics figure 7. ac electrical timing diagram 1 3 4 8 2 2 3 t irq in n 6 5 7 7 9 clock
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-13 1 ac electrical characteristics timing table (standard mode for sclk/tclk = xtal/2) t a = ?0 c to +105 c t a = 0 c to +70 c 8 mhz no. symbol parameter v cc min max units notes 1 tpc input clock period 2.0v 125 dc ns [1] 5.5v 125 dc ns [1] 2 trc,tfc clock input rise and fall times 2.0v 25 ns [1] 5.5v 25 ns [1] 3 twc input clock width 2.0v 62 ns [1] 5.5v 62 ns [1] 4 twtinl timer input low width 2.0v 70 ns [1] 5.5v 70 ns [1] 5 twtinh timer input high width 2.0v 5tpc [1] 5.5v 5tpc [1] 6 tptin timer input period 2.0v 8tpc [1] 5.5v 8tpc [1] 7 trtin, tttin timer input rise and fall time 2.0v 100 ns [1] 5.5v 100 ns [1] 8 twil int. request input low time 2.0v 70 ns [1,2,3] 5.5v 70 ns [1,2,3] 9 twih int. request input high time 3.0v 5tpc [1,2,3] 5.5v 5tpc [1,2,3] 10 twdt watch-dog timer delay time before time-out 2.0v 25 ms 3.0v 10 ms 5.5v 5 ms 11 tpor power-on reset time 2.0v 70 250 ms [4] 3.0v 50 150 ms [4] 5.5v 10 70 ms [4] 2.0v 8 76 ms [5] 3.0v 4 38 ms [5] 5.5v 2 18 ms [5] notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request through port 3 (p33-p31). 3. irq 0,1,2 only. 4. z86e02 only. 5. z86c02/l02 only.
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-14 p r e l i m i n a r y ds96dz80301 (11/96) ac electrical characteristics low noise mode (z86c02/e02 only) t a = ?0 c to +105 c t a = 0 c to +70 c 1 mhz 4 mhz no. symbol parameter v cc min max min max units notes 1 tpc input clock period 3.0v 1000 dc 250 dc ns [1] 5.5v 1000 dc 250 dc ns [1] 2trc tfc clock input rise and fall times 3.0v 25 25 ns [1] 5.5v 25 25 ns [1] 3 twc input clock width 3.0v 500 125 ns [1] 5.5v 500 125 ns [1] 4. twtinl timer input low width 3.0v 70 70 ns [1] 5.5v 70 70 ns [1] 5 twtinh timer input high width 3.0v 2.5tpc 2.5tpc [1] 5.5v 2.5tpc 2.5tpc [1] 6 tptin timer input period 3.0v 4tpc 4tpc [1] 5.5v 4tpc 4tpc [1] 7 trtin, tttin timer input rise and fall time 3.0v 100 100 ns [1] 5.5v 100 100 ns [1] 8 twil int. request input low time 3.0v 70 70 ns [1,2,3] 5.5v 70 70 ns [1,2,3] 9 twih int. request input high time 3.0v 2.5tpc 2.5tpc [1,2,3] 5.5v 2.5tpc 2.5tpc [1,2,3] 10 tpor power-on reset time 3.0v 50 150 50 150 ms [4] 5.5v 10 70 10 70 ms [4] 2.0v 8 76 8 76 ms [5] 3.0v 4 38 4 38 ms [5] 5.5v 2 18 2 18 ms [5] 11 twdt watch-dog timer delay 3.0v 10 10 ms 5.5v 5 5 ms notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request through port 3 (p33-p31). 3. irq 0,1,2 only. 4. z86e02 only. 5. z86c02/l02 only.
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-15 1 low noise version low emi emission the z8 can be programmed to operate in a low emi emis- sion mode by means of a mask rom bit option (z86c02) or otp bit option (z86e02). use of this feature results in: n all pre-driver slew rates reduced to 10 ns typical. n internal sclk/tclk operation limited to a maximum of 4 mhz - 250 ns cycle time. n output drivers have resistances of 200 ohms (typical). n oscillator divide-by-two circuitry eliminated. the low emi mode is mask-programmable to be selected by the customer at the time the rom code is submitted (for z86c02 only). precaution stack pointer register (spl) at ffhex and general purpose register at fehex are set to 00hex after reset. pin functions otp programming mode d7-d0 data bus. data can be read from, or written to the eprom through this data bus. v cc power supply. it is 5v during eprom read mode and 6.4v during the other modes (program, program ver- ify, etc.). /ce chip enable (active low). this pin is active during eprom read mode, program mode, and program verify mode. /oe output enable (active low). this pin drives the data bus direction. when this pin is low, the data bus is output. when high, the data bus is input. this pin must toggle for each data output read. epm eprom program mode. this pin controls the differ- ent eprom program modes by applying different voltages. v pp program voltage. this pin supplies the program volt- age. clear clear (active high). this pin resets the internal ad- dress counter at the high level. clock address clock. this pin is a clock input. the internal address counter increases by one with one clock cycle. /pgm program mode (active low). a low level at this pin programs the data to the eprom through the data bus. application precaution the production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above v cc occur on the xtal1 pin. in addition, processor operation of z8 otp devices may be affected by excessive noise surges on the v pp , /ce, /epm, /oe pins while the microcontroller is in standard mode. recommendations for dampening voltage surges in both test and otp mode include the following: n using a clamping diode to v cc. n adding a capacitor to the affected pin.
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-16 p r e l i m i n a r y ds96dz80301 (11/96) pin functions (continued) xtal1, xtal2 crystal in, crystal out (time-based input and output, respectively). these pins connect a parallel- resonant crystal, lc, rc, or an external single-phase clock (8 mhz max) to the on-chip clock oscillator and buff- er. port 0, p02-p00. port 0 is a 3-bit bi-directional, schmitt- triggered cmos compatible i/o port. these three i/o lines can be globally configured under software control to be in- puts or outputs (figure 8). auto latch. the auto latch puts valid cmos levels on all cmos inputs (except p33, p32, p31) that are not external- ly driven. a valid cmos level, rather than a floating node, reduces excessive supply current flow in the input buffer. on power-up and reset, the auto latch will set the ports to an undetermined state of 0 or 1. default condition is auto latches enabled. figure 8. port 0 con?uration open out in 1.5 2.3 hysteresis pa d port 0 (i/o) z8 auto latch option r 500 k w vcc @ 5.0v
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-17 1 port 2, p27-p20. port 2 is an 8-bit, bit programmable, bi- directional, schmitt-triggered cmos compatible i/o port. these eight i/o lines can be configured under software control to be inputs or outputs, independently. bits pro- grammed as outputs can be globally programmed as ei- ther push-pull or open-drain (figure 9). figure 9. port 2 con?uration open-drain open out in 1.5 2.3 hysteresis pa d port 2 (i/o) port 2 z8 auto latch option r 500 k w vcc @ 5.0v
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-18 p r e l i m i n a r y ds96dz80301 (11/96) pin functions (continued) port 3, p33-p31. port 3 is a 3-bit, cmos compatible port with three fixed input (p33-p31) lines. these three input lines can be configured under software control as digital schmitt-trigger inputs or analog inputs. these three input lines are also used as the interrupt sources irq0-irq3 and as the timer input signal t in (fig- ure 10). comparator inputs. two analog comparators are added to input of port 3, p31 and p32, for interface flexibility. the comparators reference voltage p33 (ref) is common to both comparators. typical applications for the on-board comparators; zero crossing detection, a/d conversion, voltage scaling, and threshold detection. in analog mode, p33 input functions serve as a reference voltage to the comparators. the dual comparator (common inverting terminal) features a single power supply which discontinues power in stop mode. the common voltage range is 0-4 v when the v cc is 5.0 v; the power supply and common mode rejection ra- tios are 90 db and 60 db, respectively. interrupts are generated on either edge of comparator 2's output, or on the falling edge of comparator 1's output. the comparator output is used for interrupt generation, port 3 data inputs, or t in through p31. alternatively, the comparators can be disabled, freeing the reference input (p33) for use as irq1 and/or p33 input. figure 10. port 3 con?uration port 3 z8 d1 r247 = p3m p31 (an1) p32 (an2) p33 (ref) cc dig. an. + - + - v tin p31 data latch irq2 irq3 p32 data latch irq0 p33 data latch irq1 pa d pa d pa d 0 = digital 1 = analog irq 0,1,2 = falling edge detection irq3 = rising edge detection
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-19 1 functional description the following special functions have been incorporated into the z86c02/e02/l02 devices to enhance the standard z8 core architecture to provide the user with increased de- sign flexibility. reset. this function is accomplished by means of a pow- er-on reset or a watch-dog timer reset. upon power- up, the power-on reset circuit waits for t por ms, plus 18 clock cycles, then starts program execution at address 000c (hex) (figure 11). the control registers' reset value is shown in table 4. power-on reset (por). a timer circuit clocked by a ded- icated on-board rc oscillator is used for a por timer func- tion. the por time allows v cc and the oscillator circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot timer triggered by one of the four following conditions: n power bad to power good status n stop-mode recovery n wdt time-out n wdh time-out (in halt mode) n wdt time-out (in stop mode) watch-dog timer reset. the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt is initially enabled by executing the wdt instruction and is retriggered on subsequent execution of the wdt instruction. the timer circuit is driven by an on- board rc oscillator. if the permanent wdt option is select- ed then the wdt is enabled after reset and operates in run mode, halt mode, stop mode and cannot be dis- abled. if the permanent wdt option is not selected then the wdt, when enabled by the user's software, does not operate in stop mode, but it can operate in halt mode by using a wdh instruction. figure 11. internal reset con?uration por (cold start) p27 (stop mode) delay line t por ms 18 clk reset filter chip reset xtal osc int osc table 4. control register reset condition addr reg. d7 d6 d5 d4 d3 d2 d1 d0 comments ff spl 00000000 fe gpr 00000000 fd rp 00000000 fc flagsuuuuuuuu fb imr 0uuuuuuu fa irq uu000000 irq3 is used for positive edge detection f9 ipr uuuuuuuu f8 p01m u u u 0 u u 0 1 f7* p3m uuuuuu0 0p2 open-drain f6*p2m 11111111 inputs after reset f3 pre1 uuuuuu0 0 f2 t1 uuuuuuuu f1 tmr 00000000 note: *registers are not reset after a stop-mode recovery using p27 pin. a subsequent reset will cause these control registers to be reconfigured as shown in table 4 and the user must avoid bus contention on the port pins or it may affect device reliability.
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-20 p r e l i m i n a r y ds96dz80301 (11/96) functional description (continued) program memory. the z8 addresses up to 512 bytes of internal program memory (figure 12). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations contain six 16-bit vectors that correspond to the six available interrupts. bytes 0-511 are on-chip one- time programmable rom. register file. the register file consists of three i/o port registers, 61 general-purpose registers, and 12 control and status registers r0-r3, r4-r127 and r241-r255, re- spectively (figure 13). general-purpose registers occupy the 04h to 7fh address space. i/o ports are mapped as per the existing cmos z8. the instructions can access registers directly or indirectly through an 8-bit address field. this allows short 4-bit register addressing using the register pointer. in the 4-bit mode, the register file is divid- ed into eight working register groups, each occupying 16 continuous locations. the register pointer (figure 14) ad- dresses the starting location of the active working-register group. figure 12. program memory map 12 11 10 9 8 7 6 5 4 3 2 1 0 on-chip rom location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 1024 figure 13. register file spl stack pointer (bits 7-0) reserved register pointer program control flags interrupt mask register interrupt request register interrupt priority register ports 0-1 mode port 3 mode port 2 mode to prescaler timer/counter0 t1 prescaler timer/counter1 timer mode not implemented general purpose registers port 3 port 2 reserved port 0 rp imr irq ipr p3m p2m pre0 t0 pre1 t1 tmr p3 p2 p1 p0 p01m flags indentifiers location 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 4 3 2 1 0 128 127
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-21 1 stack pointer. the z8 has an 8-bit stack pointer (r255) used for the internal stack that resides within the 60 gen- eral-purpose registers. it is set to 00hex after any reset. general-purpose registers (gpr). these registers are undefined after the device is powered up. the registers keep their last value after any reset, as long as the reset occurs in the v cc voltage-specified operating range. note: register r254 has been designated as a general-purpose register. but is set to 00hex after any reset. counter/timer. there is an 8-bit programmable counter/timers (t1), each driven by its 6-bit programmable prescaler. the t1 prescaler is driven by internal or external clock sources. (figure 15). the 6-bit prescaler divide the input frequency of the clock source by any integer number from 1 to 64. the prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. when both counter and prescaler reach the end of count, a timer interrupt re- quest irq5 (t1) is generated. the counter can be programmed to start, stop, restart to continue, or restart from the initial value. the counters are also programmed to stop upon reaching zero (single-pass mode) or to automatically reload the initial value and con- tinue counting (modulo-n continuous mode). the counter, but not the prescaler, is read at any time with- out disturbing its value or count mode. the clock source for t1 is user-definable and is either the internal microproces- sor clock divided by four, or an external signal input through port 3. the timer mode register configures the ex- ternal timer input (p31) as an external clock, a trigger input that is retriggerable or non-retriggerable, or used as a gate input for the internal clock. figure 14. register pointer the upper nibble of the register file address provided by the register pointer specifies the active working-register group. r7 r6 r5 r4 r253 (register pointer) i/o ports specified working register group the lower nibble of the register file address provided by the instruction points to the specified register. r3 r2 r1 r0 register group 1 register group 0 r15 to r0 register group f r15 to r4 r3 to r0 r15 to r0 ff f0 0f 00 1f 10 2f 20 3f 30 4f 40 5f 50 6f 60 7f 70
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-22 p r e l i m i n a r y ds96dz80301 (11/96) functional description (continued) interrupts. the z8 has five interrupts from four different sources. these interrupts are maskable and prioritized (figure 16). the sources are divided as follows: the falling edge of p31 (an1), p32 (an2), p33 (ref), the rising edge of p32 (an2), and one counter/timer. the interrupt mask register globally or individually enables or disables the five interrupt requests (table 5). when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the interrupt priority register. all z8 interrupts are vectored through locations in program memory. when an interrupt machine cycle is activated, an interrupt request is granted. this disables all subsequent interrupts, saves the program counter and status flags, and then branches to the program memory vector location reserved for that in- terrupt. this memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests needs service. user must select any z86e08 mode in zilog's c12 ice- box emulator. the rising edge interrupt is not directly supported on the z86ccp00zem emulator. figure 15. counter/timers block diagram osc ? 2 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register clock logic irq5 internal data bus write write read internal clock gated clock triggered clock t p31 external clock internal clock ? 4 in * table 5. interrupt types, sources, and vectors vector name source location comments irq0 an2(p32) 0,1 external (f)edge irq1 ref(p33) 2,3 external (f)edge irq2 an1(p31) 4,5 external (f)edge irq3 an2(p32) 6,7 external (r)edge irq4 reserved 8,9 reserved irq5 t1 10,11 internal notes: f = falling edge triggered r = rising edge triggered
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-23 1 clock. the z8 on-chip oscillator has a high-gain, parallel- resonant amplifier for connection to a crystal, ceramic res- onator, or any suitable external clock source (xtal1 = in- put, xtal2 = output). the crystal should be at cut, 8 mhz max, with a series resistance (rs) of less than or equal to 100 ohms. the crystal or ceramic resonator should be connected across xtal1 and xtal2 using the vendors crystal or ce- ramic resonator recommended capacitors from each pin directly to device ground pin 14 (figure 17). note that the crystal capacitor loads should be connected to v ss , pin 14 to reduce ground noise injection. figure 16. interrupt block diagram irq0 - irq5 irq imr ipr priority logic 5 global interrupt enable vector select interrupt request figure 17. oscillator con?uration xtal1 xtal2 c1 c2 c1 c2 ceramic resonator or crystal external clock l lc clock xtal1 xtal2 xtal1 xtal2 ** * =device ground pin xtal1 xtal2 r rc clock vss * vss * c vss *
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-24 p r e l i m i n a r y ds96dz80301 (11/96) functional description (continued) halt mode. this instruction turns off the internal cpu clock but not the crystal oscillation. the counter/timer and external interrupts irq0, irq1, irq2 and irq3 remain ac- tive. the device is recovered by interrupts, either external- ly or internally generated. an interrupt request must be ex- ecuted (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt. stop mode. this instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 m a. the stop mode is released by a reset through a stop-mode recovery (pin p27). a low input condition on p27 releases the stop mode. program exe- cution begins at location 000c(hex). however, when p27 is used to release the stop mode, the i/o port mode reg- isters are not reconfigured to their default power-on condi- tions. this prevents any i/o, configured as output when the stop instruction was executed, from glitching to an un- known state. to use the p27 release approach with stop mode, use the following instruction: in order to enter stop or halt mode, it is necessary to first flush the instruction pipeline to avoid suspending exe- cution in mid-instruction. to do this, the user executes a nop (opcode=ffh) immediately before the appropriate sleep instruction, i.e.: watch-dog timer (wdt). the watch-dog timer is en- abled by instruction wdt. when the wdt is enabled, it cannot be stopped by the instruction. with the wdt in- struction, the wdt is refreshed when it is enabled within every 1 twdt period; otherwise, the controller resets itself, the wdt instruction affects the flags accordingly; z=1, s=0, v=0. wdt = 5f (hex) opcode wdt (5fh). the first time opcode 5fh is execut- ed, the wdt is enabled and subsequent execution clears the wdt counter. this must be done at least every t wdt ; otherwise, the wdt times out and generates a reset. the generated reset is the same as a power-on reset of t por , plus 18 xtal clock cycles.the wdt does not run in stop mode, unless the permanent wdt enable option is select- ed. the wdt does not run in halt mode unless wdh in- struction is executed or permanent wdt enable option is selected. opcode wdh (4fh). when this instruction is executed it enables the wdt during halt. if not, the wdt stops when entering halt. this instruction does not clear the counters, it just makes it possible to have the wdt running during halt mode. a wdh instruction executed without executing wdt (5fh) has no effect. note: opcode wdh and permanently enabled wdt is not directly supported by the z86ccp00zem. auto reset voltage (v lv ). the z8 has an auto-reset built- in. the auto-reset circuit resets the z8 when it detects the v cc below v lv . figure 18 shows the auto reset voltage versus temperature. ld p2m, #1xxx xxxxb nop stop notes: x = dependent on user? application. stop-mode recovery pin p27 is not edge triggered. ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-25 1 options the z86c02/e02/l02 offers rom protect, low noise, auto latch disable, rc oscillator, and permanent wdt enable features as options. the z86e02 must be power cycled to fully implement the selected option after pro- gramming. low noise. the z8 can operate in a low emi emission mode by selecting the low noise option. use of this feature will result in: n all drivers slew rates are reduced to 10 ns (typical). n internal sclk/tclk = xtal operation is limited to a maximum of 4 mhz - 250 ns cycle time. n output drivers have resistances of 200 ohms (typical). n oscillator divide-by-two circuitry is eliminated. rom protect. rom protect fully protects the z8 rom code from being read externally. when rom protect is se- lected, the instructions ldc and ldci are supported. (however, instructions lde and ldei are not supported.) eprom/test mode disable. when selected, this bit will permanently disable eprom and factory test mode. auto latch disable. auto latch disable option when se- lected will globally disable all auto latches. rc. rc oscillator option when selected will allow using a resistor (r) and a capacitor (c) as a clock source. wdt enable. wdt enable option bit when selected will have the wdt permanently enabled in all modes and can not be stopped in halt or stop mode. eprom mode description. in addition to v dd and gnd (v ss ), the z8 changes all its pin functions in the eprom mode. xtal2 has no function, xtal1 functions as /ce, p31 functions as /oe, p32 functions as epm, p33 func- tions as v pp , and p02 functions as /pgm. please note that when using the device in a noisy environ- ment, it is suggested that the voltages on the epm and ce pins be clamped to v cc through a diode to v cc to prevent accidentally entering the otp mode. the v pp requires both a diode and a 100 pf capacitor. user modes. table 6 shows the programming voltage of each mode of z86e02. figure 18. typical auto reset voltage (v lv ) vs. temperature 2.6 2.7 2.8 2.9 3.0 3.2 vcc (volts) C40 c 40 c temp 2.5 C20 c0 c20 c 60 c80 c 100 c 3.1 1.8 1.9 2.0 2.1 2.2 2.4 1.7 2.3 1.6 z86e02 z86l02 z86c02
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-26 p r e l i m i n a r y ds96dz80301 (11/96) functional description (continued) internal address counter. the address of z86e02 is generated internally with a counter clocked through pin p01 (clock). each clock signal increases the address by one and the "high" level of pin p00 (clear) will reset the ad- dress to zero. figure 19 shows the setup time of the serial address input. programming waveform. figures 20, 21, 22, and 23 show the programming waveforms of each mode. table 7 shows the timing of programming waveforms. programming algorithm. figure 24 shows the flow chart of the z86e02 programming algorithm. table 6. eprom programming table programming modes v pp epm /ce /oe /pgm addr data v cc * eprom read nu v h v il v il v ih addr out 5.0v program v h v ih v il v ih v il addr in 6.4v program verify v h v ih v il v il v ih addr out 6.4v rom protect v h v h v h v ih v il nu nu 5.0-6.4v low noise select v h v ih v h v ih v il nu nu 5.0-6.4v auto latch disable v h v ih v h v il v il nu nu 5.0-6.4v wdt enable v h v il v h v ih v il nu nu 5.0-6.4v eprom/test mode disable v h v il v h v il v il nu nu 5.0-6.4v notes: v h =13.0v 0.25 v dc . v ih =as per specific z8 dc specification. v il =as per specific z8 dc specification. x=not used, but must be set to v h , v ih , or v il level. nu=not used, but must be set to either v ih or v il level. i pp during programming = 40 ma maximum. i cc during programming, verify, or read = 40 ma maximum. * v cc has a tolerance of 0.25v. table 7. z86e02 timing of programming waveforms parameters name min max units 1 address setup time 2 m s 2 data setup time 2 m s 3v pp setup 2 m s 4v cc setup time 2 m s 5 chip enable setup time 2 m s 6 program pulse width 0.95 ms 7 data hold time 2 m s 8 /oe setup time 2 m s 9 data access time 188 4000 ns 10 data output float time 100 ns 11 over-program pulse width 2.85 3.2 ms 12 epm setup time 2 m s 13 /pgm setup time 2 m s 14 address to /oe setup time 2 m s 15 option program pulse width 150 ms 16 /oe low width 250 ns
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-27 1 figure 19. z86e02 address counter waveform p01 = clock p00 = clear t2 t4 t3 t1 internal address t5 0 min 9 data vih vil invalid valid invalid valid legend: t1 reset clock width t2 input clock high t3 input clock period t4 input clock low t5 clock to address counter out delay 30 ns min 30 ns min 70 ns min 30 ns min 15 ns max
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-28 p r e l i m i n a r y ds96dz80301 (11/96) functional description (continued) figure 20. z86e02 programming waveform (eprom read) data vih vil invalid valid invalid valid vih vil address stable address address stable 0 min 9 12 0 min epm vh vil vcc 5v /ce vih vil /oe vih vil vpp vh vih /pgm vih vil 3 16 16
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-29 1 figure 21. z86e02 programming waveform (program and verify) address vih vil data vih vil vpp vih vcc 6.4v 3 4 5 /ce vh vih /pgm vih vil 12 15 15 epm vil auto latch wdt 15 etm disable 5v vih vil vh 8 /oe vil vih 8 vil 12
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-30 p r e l i m i n a r y ds96dz80301 (11/96) functional description (continued) figure 22. z86e02 programming options waveform (rom protect and low noise program) address v ih v il data v ih v il v pp v ih v cc 6.4v /oe 3 4 5 /ce v h v ih /pgm v ih v il 12 15 15 epm v ih rom protect low noise 5v v il v il v ih v h 12 v h v ih
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-31 1 figure 23. z86e02 programming options waveform (auto latch disable, permanent wdt enable, and eprom/test mode disable) address vih vil data vih vil vpp vih vcc 6.4v 3 4 5 /ce vh vih /pgm vih vil 12 15 15 epm vil auto latch wdt 15 etm disable 5v vih vil vh 8 /oe vil vih 8 vil 12
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-32 p r e l i m i n a r y ds96dz80301 (11/96) functional description (continued) figure 24. z86e02 programming algorithm start vcc = 6.4v vpp = 13.0v n = 0 program 1 ms pulse increment n n = 25 ? ye s no verify one byte pass fail prog. one pulse 3xn ms duration verify byte fail pass increment address last addr ? ye s no vcc = vpp = 5.0v verify all bytes device failed addr = first location fail pass device passed
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-33 1 z8 control registers figure 25. timer mode register (f1 h : read/write) figure 26. counter timer 1 register (f2 h :read/write) figure 27. prescaler! register (f3 h : write only) figure 28. port 2 mode register (f6 h : write only) d7 d6 d5 d4 d3 d2 d1 d0 0 disable t count 1 enable t count reserved (must be 0) 0 0 0 no function 1 load t 1 0 disable t count 1 enable t count 1 1 t modes 00 external clock input 01 gate input 10 trigger input (non-retriggerable) 11 trigger input (retriggerable) in r241 tmr reserved (must be 0.) d7 d6 d5 d4 d3 d2 d1 d0 t initial value (when written) (range 1-256 decimal 01-00 hex) t current value (when read) 1 1 r242 t1 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 = t single pass 1 = t modulo n 1 1 clock source 1 = t internal 0 = t external timing input (t ) mode in 1 1 prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1 d7 d6 d5 d4 d3 d2 d1 d0 p2 - p2 i/o definition 0 defines bit as output 1 defines bit as input 70 r246 p2m figure 29. port 3 mode register (f7 h : write only) figure 30. port 0 and 1 mode register (f8 h : write only) figure 31. interrupt priority register (f9 h : write only) d7 d6 d5 d4 d3 d2 d1 d0 0 port 2 open-drain 1 port 2 push-pull port 3 inputs 0 digital mode 1 analog mode reserved (must be 0) r247 p3m d7 d6 d5 d4 d3 d2 d1 d0 p0 3 -p0 0 mode 00 = output 01 = input reserved (must be 1.) r248 p01m reserved (must be 0.) d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b > c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved irq3, irq5 priority (group a) 0 irq5 > irq3 1 irq3 > irq5 irq0, irq2 priority (group b) 0 irq2 > irq0 1 irq0 > irq2 irq1, irq4 priority (group c) 0 irq1 > irq4 1 irq4 > irq1 reserved (must be 0.) r249 ipr
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-34 p r e l i m i n a r y ds96dz80301 (11/96) z8 control registers (continued) figure 32. interrupt request register (fa h : read/write) figure 33. interrupt mask register (fb h : read/write) figure 34. flag register (fc h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = p32 input - irq4 = reserved irq5 = t1 reserved (must be 0.) r250 irq d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0.) 1 enables irq5-irq0 (d = irq0) 1 enables interrupts 0 r251 imr d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag r252 flags figure 35. register pointer fd h : read/write) figure 36. stack pointer (ff h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0.) register pointer r253 rp d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp - sp ) 0 7 r255 spl
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers ds96dz80301 (11/96) p r e l i m i n a r y 1-35 1 package information figure 37. 18-pin dip package diagram figure 38. 18-pin soic package diagram
z86c02/e02/l02 low-cost, 512-byte rom microcontrollers 1-36 p r e l i m i n a r y ds96dz80301 (11/96) ordering information for fast results, contact your local zilog sales office for assistance in ordering the part(s) desired. codes preferred package p = plastic dip longer lead time s = soic preferred temperature s = 0 c to +70 c e = ?0 c to +105 c speed 08 = 8 mhz environmental c = plastic standard standard temperature 18-pin dip 18-pin soic Z86E0208PSC z86e0208ssc z86l0208psc z86l0208ssc z86c0208psc z86c0208ssc Z86E0208PSC1903 z86e0208ssc1903 extended temperature 18-pin dip 18-pin soic z86e0208pec z86e0208sec z86l0208pec z86l0208sec z86c0208pec z86c0208sec z86e0208pec1903 z86e0208sec1903 example: z 86e08 08 p s c is a z86e08, 08 mhz, dip, 0 to +70 c, plastic standard flow environmental flow temperature package speed product number zilog pre?

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